Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (post-index, 1D)

Test 1: uops

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.003

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005298496048100330412004100230062000300060002305160002000300030006000100120003000
65004295236004100130032000100030002002300360472310760062002300330006000100120003000
65004296126004100130032000100030002000300060002303060002000300030006000100120003000
65004296156004100130032000100030002000300060002303060002000300030006000100120003000
65004296326004100130032000100030002000300060002303060002000300030006000100120003000
65004296896004100130032000100030002000300060002303060002000300030006000100120003000
65004296476004100130032000100030002000300060002303060002000300030006000100120003000
65004296276004100130032000100030002000300060002303060002000300030006000100120003000
65004296546004100130032000100030002002300361042320260062002300330006000100120003000
65004297776010100230062002100130032002300360062305460062002300330036006100220003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4002051601614802408011524009716002880115240037160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024005748011080017160000240000100
4002041600564801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312482006192350948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024005748011080017160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160038240355481380192293748021220016003824005520024001248002280004160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4000251601584801508002524009716002880025240037160008240042480036192054248003320160008240011202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000251600814801168002724005716003280028240053160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400544801068001716000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010
4000241600374800298001124001816000080010240000160000240030480022192025648001020160000240000202400004800008000116000024000010