Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (post-index, 2D)

Test 1: uops

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.006

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005297086048100330412004100230062000300060002305760002000300030006000100120003000
65004294926007100130062000100030002000300060002305760002000300030006000100120003000
65004294606007100130062000100030002000300060002305760002000300030006000100120003000
65004294636007100130062000100030002000300060002305760002000300030006000100120003000
65004294656007100130062000100030002000300060002305760002000300030006000100120003000
65004294916007100130062000100030002000300060002305760002000300030006000100120003000
65004294936007100130062000100030002000300060002305760002000300030006000100120003000
65004297586007100130062000100030002000300060002305760002000300030006000100120003000
65004294606007100130062000100030002000300060002305760002000300030006000100120003000
65004294656007100130062000100030002000300060002305760002000300030006000100120003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3r { v0.2d, v1.2d, v2.2d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4002051601474802408011524009716002880115240037160008240312480046192007348012320016000824001120024005448010680017160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160008240312480046192006948012320016000824001120024001248002280004160000240000100
4002041600444801418010424003116000680104240011160036240353480128192036548020720016003624005320024001248002280004160000240000100
4002041600454801418010424003116000680104240011160008240312480336192041348012320016000824001120024001248002280004160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4000251601584801508002524009716002880025240037160000240030480012192047148001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160028240071480116192105948009420160028240042202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010
4000251600944801528002724009316003280028240053160000240030480012192046748001020160000240000202400004800008000116000024000010
4000241600434800388001124002716000080010240000160000240030480012192046748001020160000240000202400004800008000116000024000010