Icestorm: LD3R (post-index, 2S) measurements

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29855	5046	1003	3041	1002	1002	3006	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29541	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29540	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29674	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29495	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29536	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29505	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29543	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29495	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000
64004	29525	5007	1001	3006	1000	1000	3000	1000	3000	3000	23051	5000	1000	3000	2000	3000	1001	1000	3000

Count: 8

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	120295	400197	80114	240070	80013	80114	240036	80004	240312	240015	1701668	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120062	400133	80104	240026	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240032	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160052	240078	80025	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120054	400129	80104	240022	80003	80104	240010	80004	240312	240015	2400440	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	120292	400107	80024	240070	80013	80024	240036	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240100	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320025	120090	400123	80035	240064	80024	80035	240073	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10

LD3R (post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations