Icestorm: LD3R (post-index, 4H) measurements

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.003

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29601	5046	1003	3041	1002	1002	3006	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29429	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29419	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2002	3003	1002	1000	3000
64004	29418	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29445	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29416	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29443	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29425	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29423	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000
64004	29445	5004	1001	3003	1000	1000	3000	1000	3000	3000	23036	5000	1000	3000	2000	3000	1001	1000	3000

Count: 8

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	120157	400197	80114	240070	80013	80114	240036	80004	240312	240015	2119334	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80025	240375	240078	1712062	400223	200	80026	240078	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120068	400122	80104	240015	80003	80104	240010	80004	240312	240194	2400302	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320204	120048	400122	80104	240015	80003	80104	240010	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100
320205	120092	400214	80125	240065	80024	80126	240074	80004	240312	240015	2400284	400118	200	80005	240015	200	160010	240015	80004	80000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	120175	400111	80024	240074	80013	80024	240036	80004	240042	240016	2040228	400028	20	80005	240015	20	160000	240000	80001	80000	240000	10
320024	120046	400031	80014	240014	80003	80014	240010	80026	240108	240086	2401005	400136	20	80026	240078	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80004	240042	240016	2400242	400028	20	80005	240015	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80025	240105	240082	2400908	400133	20	80026	240078	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10
320024	120046	400025	80011	240014	80000	80010	240000	80000	240030	240004	2400180	400010	20	80000	240000	20	160000	240000	80001	80000	240000	10

LD3R (post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations