Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (multiple, 16B)

Test 1: uops

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.002

Integer unit issues: 0.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660052985760311302430063006300090002455160003000300030009000130003000
660042968960051300430003000300090062453660003000300030009000130003000
660042980560031300230003000300090022453360003000300030009000130003000
660042987760031300230003000300090002453060003000300030009000130003000
660042960660031300230003000300090062453660003000300030009000130003000
660042962160031300230003000300090002453060003000300030109018130003000
660042963160031300230003000300090002453060003000300030009000130003000
660042960460031300230003000300090002453060003000300030009000130003000
660042967860091300530033003300090142454560003000300030009000130003000
660042960660031300230003000300090002453060003000300030009000130003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020516017348017610124003724003810024003624001130072016720802114801212002400122400102002400127200301240000240000100
48020416005848012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400547201501240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100
48020516008948018610124004724003810024005024005330072079120810724802032002400542400502002400127200301240000240000100
48020416004648012610124001724000810024001024001130072016720802094801212002400122400102002400127200301240000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516015948008611240037240038102400362400113072016720805934800312024001224001020240000720000124000024000010
48002516010048009611240047240038102400502400003072017920805284800102024000024000020240000720000124000024000010
48002416005048002311240012240000102400002400003072015520804984800102024000024000020240000720000124000024000010
44467521540444361815691209774218153155812097792400003072059120810084800102024000024000020240000720000124000024000010
48002416005048002311240012240000102400002400003072015520804984800102024000024000020240000720000124000024000010
48002416005048002311240012240000102400002400003072015520804984800102024000024000020240000720000124000024000010
48002416005048002311240012240000102400002400003072015520804984800102024000024000020240054720150124000024000010
48002416005048002311240012240000102400002400113072437420851684800312024001224001020240000720000124000024000010
48002416005048002311240012240000102400002400003072015520804984800102024000024000020240000720000124000024000010
48002416005048002311240012240000102400002400003072018520805284800102024000024000020240000720000124000024000010