Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (multiple, 2S)

Test 1: uops

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.006

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052983450451304020043006200060002305150002000300020006000120003000
650042953950071300620003000200060002305150002000300020006000120003000
650042953250071300620003000200060002305150002000300020006000120003000
650042957250071300620003000200060002305150002000300020006000120003000
650042953250071300620003000200060002305150002000300020006000120003000
650042953050071300620003000200060042305750002000300020006000120003000
650042985950071300620003000200060002305150002000300020006000120003000
650042984550071300620003000200060002305650002000300020006000120003000
650042978650071300620003000200060002305250002000300020006000120003000
650042988650071300620003000200060002305550002000300020006000120003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020516016440022610124009716002810024003716000830048003619201864001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116000830048003619201784001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116003230048010419204144001782001600322400462001600084800221160000240000100
40020416004440014010124003316000610024001116003230048012619208814001782001600322400462001600084800221160000240000100
40020416004440014010124003316000610024001116000830048010219202904001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116000830048003619201784001192001600082400112001600084800221160000240000100
40020516008040018610124005916002610024004616000830048003619202304001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116000830048004219201884001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116000830048004819202024001192001600082400112001600084800221160000240000100
40020416004440014010124003316000610024001116000830048004819202004001192001600082400112001600084800221160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002516015840013611240097160028102400371600003048002219203624000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002516007340008411240047160026102400461600003048001619201904000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160032480092116000024000010
40002416003940003211240021160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010
40002416003640002611240015160000102400001600003048001619201864000102016000024000020160000480000116000024000010