Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (multiple, 4H)

Test 1: uops

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.003

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052974850461304120043006200060002303650002000300020006000120003000
650042983950041300320003000200060002303650002000300020026000120003000
650042997350041300320003000200060002303050002000300020006000120003000
650043020950041300320003000200060002303050002000300020006000120003000
650043009450041300320003000200060572312050002000300020006000120003000
650043001750041300320003000200060002303050002000300020006000120003000
650042992050041300320003000200060002303050002000300020006000120003000
650042956550041300320003000200060002303050002000300020006000120003000
650042956550041300320003000200060002303050002000300020006000120003000
650042956650041300320003000200060002303050002000300020006000120003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020516014640022610124009716002810024003716000830048004619200774001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116003230048010819201334001782001600322400462001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020516007340017410124004716002610024004616000830048007619199614001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002516014040013611240097160028102400371600083048003619205424000292016000824001120160000480000116000024000010
40002516007940008411240053160020102400351600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160032480092116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416007940006911240052160006102400111600003048002219203624000102016000024000020160000480000116000024000010
40002416004140003611240025160000102400001600323048028619209674000882016003224004620160000480000116000024000010
40002416004140003611240025160000102400001600003048002219203584000102016000024000020160000480000116000024000010