Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (multiple, 8B)

Test 1: uops

Code:

  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.003

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650053002650451304020043006200060002303050002000300020006000120003000
650042992350041300320003000200060002303050002000300020006000120003000
650042976050041300320003000200060002303050002000300020006000120003000
650042975850041300320003000200060002303050002000300020006000120003000
650042975650041300320003000200060002303050002000300020006000120003000
650042977350041300320003000200060002303050002000300020006000120003000
650042975650041300320003000200060002303050002000300020006000120003000
650042977350041300320003000200060002303050002000300020006000120003000
650042977450041300320003000200060002303050002000300020006000120003000
650042976550041300320003000200060002303050002000300020006000120003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020516035240022610124009716002810024003716000830048003619201864001192001600082400112001600084800221160000240000100
40020416037340037610124017316010210024015116000830048003619201784001192001600082400112001600084800221160000240000100
40020416036840036910324016416010210224015116000830048003619201784001192001600082400112001600324800921160000240000100
40020416004040013410124002716000610024001116010430048330019257964003552001601042401512001600084800221160000240000100
40020416003840013110124002416000610024001116010430048325219257724003552001601042401512001600084800221160000240000100
40020416003840013110124002416000610024001116000830048003619201784001192001600082400112001600084800221160000240000100
40020416003840013110124002416000610024001116000830048003619201784001192001600082400112001600084800221160000240000100
40020416013240019210124006116003010024004616003230048010419204144001782001600322400462001600084800221160000240000100
40020416003840013110124002416000610024001116003230048037819208944001782001600322400462001600084800221160000240000100
40020416036840036710124016416010210024015116000830048003619201784001192001600082400112001600084800221160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002516016240013611240097160028102400371600083048003619205424000292016000824001120160008480022116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600323048010419207744000882016003224004620160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010
40002516008040010511240068160026102400461600003048001219204674000102016000024000020160000480000116000024000010
40002416004340003811240027160000102400001600003048001219204674000102016000024000020160000480000116000024000010