Icestorm: LD3 (multiple, post-index, 16B) measurements

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.002

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66005	29738	7033	1003	3024	3006	1002	3006	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29516	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29524	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29523	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29540	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29527	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29523	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29523	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29540	7003	1001	3002	3000	1000	3000	3000	3000	9000	24536	7000	3000	3000	4000	9000	1001	3000	3000
66004	29835	7003	1001	3002	3000	1000	3000	3000	3000	9003	24539	7000	3000	3000	4004	9009	1002	3000	3000

Count: 8

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480205	160168	560190	80115	240037	240038	80115	240036	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160057	560127	80104	240015	240008	80104	240010	240011	240312	720170	2080151	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160045	560127	80104	240015	240008	80104	240010	240053	240354	720263	2080253	560221	200	240054	240050	200	320016	720030	80004	240000	240000	100
480204	160045	560127	80104	240015	240008	80104	240010	240011	240312	720200	2080184	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160073	560129	80104	240017	240008	80104	240010	240011	240312	720208	2080193	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160045	560127	80104	240015	240008	80104	240010	240011	240312	720170	2080149	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160045	560127	80104	240015	240008	80104	240010	240011	240312	720170	2080149	560125	200	240012	240010	200	320072	720150	80018	240000	240000	100
480204	160046	560127	80104	240015	240008	80104	240010	240011	240312	720170	2080149	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480205	160098	560203	80120	240045	240038	80120	240050	240011	240312	720170	2080151	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160045	560127	80104	240015	240008	80104	240010	240011	240312	720170	2080151	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480025	160310	560100	80025	240037	240038	80025	240036	240000	240030	720152	2080563	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320072	720150	80018	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320056	720120	80015	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240000	240030	720152	2080561	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160051	560023	80011	240012	240000	80010	240000	240053	240084	720415	2081012	560131	20	240054	240050	20	320000	720000	80001	240000	240000	10

LD3 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations