Icestorm: LD3 (multiple, post-index, 2D) measurements

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.004

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66005	30048	7059	1006	3038	3015	1005	3015	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29925	7005	1001	3004	3000	1000	3000	3000	3000	9000	24566	7000	3000	3000	4000	9000	1001	3000	3000
66004	29884	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29640	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29628	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29628	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29633	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29628	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000
66004	29629	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4004	9006	1001	3000	3000
66004	29637	7005	1001	3004	3000	1000	3000	3000	3000	9000	24557	7000	3000	3000	4000	9000	1001	3000	3000

Count: 8

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480205	160180	560190	80115	240037	240038	80115	240036	240011	240312	720188	2080390	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160066	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080390	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480205	160103	560203	80118	240047	240038	80118	240050	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320072	720150	80018	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320072	720150	80018	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100
480204	160054	560129	80104	240017	240008	80104	240010	240011	240312	720188	2080388	560125	200	240012	240010	200	320016	720030	80004	240000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480025	160180	560100	80025	240037	240038	80025	240036	240011	240042	720282	2081159	560035	20	240012	240010	20	320016	720030	80004	240000	240000	10
480024	160040	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080260	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160041	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080262	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160049	560023	80011	240012	240000	80010	240000	240000	240030	720137	2080262	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160049	560023	80011	240012	240000	80010	240000	240000	240030	720155	2080499	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160041	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080260	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160041	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080262	560010	20	240000	240000	20	320072	720150	80018	240000	240000	10
480024	160040	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080262	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160040	560021	80011	240010	240000	80010	240000	240000	240030	720137	2080260	560010	20	240000	240000	20	320000	720000	80001	240000	240000	10
480024	160056	560039	80014	240017	240008	80014	240010	240011	240042	720170	2080333	560035	20	240012	240010	20	320000	720000	80001	240000	240000	10

LD3 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations