Icestorm: LD3 (multiple, post-index, 4H) measurements

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.003

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
65005	29813	6048	1003	3041	2004	1002	3006	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29830	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29691	6004	1001	3003	2000	1000	3000	2000	3000	6004	23036	6000	2000	3000	3000	6000	1001	2000	3000
65004	29613	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29581	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29618	6004	1001	3003	2000	1000	3000	2000	3000	6000	23042	6000	2000	3000	3000	6000	1001	2000	3000
65004	29618	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29575	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29615	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000
65004	29576	6004	1001	3003	2000	1000	3000	2000	3000	6000	23030	6000	2000	3000	3000	6000	1001	2000	3000

Count: 8

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3 { v0.4h, v1.4h, v2.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400205	160312	480241	80115	240098	160028	80115	240037	160008	240312	480046	1920073	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160068	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240054	480106	80017	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160038	240355	481290	1922419	480212	200	160038	240055	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100
400204	160044	480141	80104	240031	160006	80104	240011	160008	240312	480046	1920069	480123	200	160008	240011	200	240012	480022	80004	160000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400025	160154	480150	80025	240097	160028	80025	240037	160038	240085	480132	1920711	480122	20	160038	240055	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400025	160089	480145	80027	240086	160032	80029	240055	160000	240030	480246	1920662	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240057	480110	80017	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10
400024	160037	480029	80011	240018	160000	80010	240000	160000	240030	480022	1920256	480010	20	160000	240000	20	240000	480000	80001	160000	240000	10

LD3 (multiple, post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations