Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (multiple, post-index, 4S)

Test 1: uops

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.004

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
66005297977033100330243006100230063000300090002455170003000300040009000100130003000
66004295997005100130043000100030003000300090002455170003000300040009000100130003000
66004295917005100130043000100030003000300090002455170003000300040009000100130003000
66004301077005100130043000100030003000300090092456570003000300040009000100130003000
66004296647005100130043000100030003000300090002455170003000300040009000100130003000
66004295667005100130043000100030003000300090002455170003000300040009000100130003000
66004295617005100130043000100030003000300090002455170003000300040009000100130003000
66004295907005100130043000100030003000300090002455170003000300040049009100130003000
66004295647005100130043000100030003000300090002455170003000300040009000100130003000
66004295897005100130043000100030003000300090002455170003000300040009000100130003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4802051603165601908011524003724003880115240036240011240312720188208039456012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032001672003080004240000240000100
4802051601095602038011824004724003880118240050240011240312720334208055456012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032007272015080018240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032001672003080004240000240000100
4802051601055602098011824005324003880118240050240011240312720218208041856012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240011240312720188208038856012520024001224001020032001672003080004240000240000100
4802041600545601298010424001724000880104240010240053240354720424208077756022120024005424005020032001672003080004240000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0009

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4800251601495601008002524003724003880025240036240011240042720185208063256003520240012240010203200007200008000124000024000010
4800241600495600238001124001224000080010240000240000240030720155208049956001020240000240000203200007200008000124000024000010
4800241600495600238001124001224000080010240000240000240030720155208049956001020240000240000203200007200008000124000024000010
4800251601035601138002824004724003880028240050240000240030720155208049956001020240000240000203200007200008000124000024000010
4800241600495600238001124001224000080010240000240053240084720555208123056013120240054240050203200007200008000124000024000010
4800251601065601178002824005124003880028240050240000240030720155208049956001020240000240000203200007200008000124000024000010
4800241600495600238001124001224000080010240000240000240030720155208049956001020240000240000203200727201508001824000024000010
4800241600495600238001124001224000080010240000240000240030720155208049956001020240000240000203200007200008000124000024000010
4800241600495600238001124001224000080010240000240000240030720155208049956001020240000240000203200007200008000124000024000010
4800241600425600218001124001024000080010240000240000240030720155208049956001020240000240000203200007200008000124000024000010