Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, D)

Test 1: uops

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.006

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052981350251302020043006200060002305150002000300020009000120003000
650042969050071300620003000200060002305150002000300020009000120003000
650042994750071300620003000200060002305150002000300020009000120003000
650042954950071300620003000200060002305150002000300020009000120003000
650042955150071300620003000200060002305150002000300020009000120003000
650042995550071300620003000200060002305150002000300020009000120003000
650042975650071300620003000200060002305150002000300020009000120003000
650042966950071300620003000200060002305150002000300020009000120003000
650042960850071300620003000200060002305150002000300020009000120003000
650042978750071300620003000200060002305150002000300020009000120003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0199

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020616022540021010124006116004810024007216000830048020622924544001192001600082400112001600087200331160000240000100
40020416159240011710124001016000610024000616000630048006039146604001122001600082400112001600087200331160000240000100
40020416159240011710124001016000610024000616000630048005439146864001122001600082400112001600427201831160000240000100
40020416159440011710124001016000610024000616000630048004239146604001122001600082400112001600767203331160000240000100
40020416159240011710124001016000610024000616000630048003039146604001122001600082400112001600087200331160000240000100
40020416159240011710124001016000610024000616000630048003039146604001122001600082400112001600087200331160000240000100
40020416159240011710124001016000610024000616000630048003039146604001122001600082400112001600087200331160000240000100
400204161592400117101240010160006100240006163266159133522907368764640868970521639192401942001600087200331160000240000100
40020416159240011710124001016000610024000616000630048003039146604001122001600082400112001600087200331160000240000100
40020416159240011710124001016000610024000616000630048003039146604001122001600082400112001600087200331160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002616035240012211240061160050102400731600083048004022993464000292016000824001120160000720000116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160000720000116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160000720000116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160042720183116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160000720000116000024000010
40002416004640001611240005160000102400001600003048003438202074000102016000024000020160000720000116000024000010
40002516421040008013240031160036122400561600003048002238202074000102016000024000020160000720000116000024000010
40002416004640001611240005160000102400001600423048013827695394001132016004224006120160000720000116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160000720000116000024000010
40002416004640001611240005160000102400001600003048001638202074000102016000024000020160000720000116000024000010