Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, S)

Test 1: uops

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640052993440251302210023006100030002305140001000300010006000110003000
640042956140071300610003000100030002305140001000300010006000110003000
640042948140071300610003000100030002305140001000300010006000110003000
640042947340071300610003000100030002305140001000300010006000110003000
640042948540071300610003000100030002305140001000300010006000110003000
640042948340071300610003000100030002305140001000300010006000110003000
640052954840071300610003000100030002305140001000300010006000110003000
640042947240071300610003000100030002305140001000300010006000110003000
640042948340071300610003000100030002305140001000300010006000110003000
640042961640071300610003000100030022305740001000300010006000110003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0198

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205161698320143101240030800121002400328000330024002340284193201092008000424001220080004480024180000240000100
320204161595320114101240010800031002400078002130024011239004813201772008002224006620080004480024180000240000100
320204161587320109101240005800031002400078000430024001539001443201112008000424001220080004480024180000240000100
320204161587320109101240005800031002400078000430024001539001443201112008000424001220080004480024180000240000100
320204161587320109101240005800031002400078000430024001539001443201112008000424001220080004480024180000240000100
320204164167320108101240005800021002400068000430024001539001443201112008000424001220080004480024180000240000100
320204161587320109101240005800031002400078002130024042839004843201772008002224006620080004480024180000240000100
320204161587320109101240005800031002400078000430024002139001443201112008000424001220080022480132180000240000100
320204161587320109101240005800031002400078000430024001539001443201112008000424001220080004480024180000240000100
320204161587320109101240005800031002400078000430024001539001443201112008000424001220080022480132180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0199

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025161698320053112400308001210240033800033024001239139063200192080004240012208000048000018000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208002248013218000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320024161595320021112400108000010240000800213024041039006943200862080022240066208000048000018000024000010
320024161595320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320024161596320021112400108000010240000800003024000339003093200102080000240000208000048000018000024000010
320025161643320069112400418001710240050800003024000339003093200102080000240000208002348013818000024000010