Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, post-index, D)

Test 1: uops

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.006

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005299276027100330202004100230062000300060002306060002000300030009000100120003000
65004294906007100130062000100030002000300060002305760002000300030009000100120003000
65004294886007100130062000100030002000300060002305760002000300030009000100120003000
65004294846007100130062000100030002000300060002305760002000300030009000100120003000
65004294886007100130062000100030002000300060002305760002000300030009000100120003000
65004294856007100130062000100030002000300060002305760002000300030009000100120003000
65004294916007100130062000100030002000300060002305760002000300030009000100120003000
65004294866007100130062000100030002000300060002305760002000300030009000100120003000
65004294876007100130062000100030002000300060002305760002000300030009000100120003000
65004294896007100130062000100030002000300060002305760002000300030009000100120003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  ld3 { v0.d, v1.d, v2.d }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0721

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4002051601704801768011524003316002880115240037160008240312480046245060748012320016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160042240363480162315127148022420016004224006120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002051629024802038012124004616003680121240061160008240312480080405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100
4002041657694801158010424000516000680104240006160008240312480040405300348011820016000824001120024001272003380004160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0775

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4000251603214800888002524003516002880025240037160034240081481318314401948011120160034240050202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400637201838002116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160042240093480182402734748013020160042240061202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030480022404313748001020160000240000202400007200008000116000024000010
4000241662034800218001124001016000080010240000160000240030481678404313748001020160000240000202400007200008000116000024000010