Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, post-index, S)

Test 1: uops

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.003

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
64005296605025100330201002100230061000300030002319150001000300020006000100110003000
64004294225004100130031000100030001000300030002303650001000300020006000100110003000
64004294245004100130031000100030001000300030002303650001000300020006000100110003000
64004294135004100130031000100030001000300030002303650001000300020006000100110003000
64004294295004100130031000100030001000300030002303650001000300020006000100110003000
64004294145004100130031000100030001000300030002307350001000300020006000100110003000
64004294375004100130031000100030001000300030002303650001000300020006000100110003000
64004294415004100130031000100030001000300030002303650001000300020006000100110003000
64004294075004100130031000100030001000300030002303650001000300020006000100110003000
64004294065004100130031000100030001000300030002303650001000300020006000100110003000

Test 2: throughput

Count: 8

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0199

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205161701400157801142400308001380114240033800032403092400124032837400112200800042400122001600084800248000380000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800212403612400643900634400197200800222400662001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320205161630400175801202400368001980121240057800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600084800248000480000240000100
320204161593400117801042400108000380104240007800042403122400153900300400115200800042400122001600444801328001980000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0199

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025161692400065800232400308001280023240032800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302406964052227400010208000024000020160000480000800018000024000010
320025161630400082800292400358001880031240056800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160044480132800198000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010
320024161593400021800112400108000080010240000800002400302400033900257400010208000024000020160000480000800018000024000010