Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (16B)

Test 1: uops

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052990850531405010024008100030003056850001000400010004000110004000
650042953250091400810004000100030003056850001000400010004000110004000
650042953650091400810004000100030003056850001000400010004000110004000
650042953750091400810004000100030003056850001000400010004000110004000
650042987150091400810004000100030003056850001000400010004000110004000
650042958450091400810004000100030003056850001000400010004000110004000
650042980150091400810004000100030003057250001000400010004000110004000
650043031550091400810004000100030003056850001000400010004000110004000
650042981550091400810004000100030003057650001000400010004000110004000
650042989950091400810004000100030003056850001000400010014004110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160235400202101320090800111003200398000430024006428346064001172008000432001520080004320015180000320000100
400204160064400140101320036800031003200138000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400205160090400187101320070800161003200678000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080018320071180000320000100
400204160054400132101320028800031003200128003230024047130353984002522008003232012720080004320015180000320000100
400204160055400132101320028800031003200128000430024002232004524001162008000432001520080004320015180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160157400110113200888001110320038800043024002527364584000272080004320015208001832007118000032000010
400025160115400090113200648001510320064800003024001532002204000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000432002164000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800183024041832009664000942080018320071208000032000018000032000010
400024160048400035113200248000010320000800183024005731131364000952080018320071208000032000018000032000010
400024160059400039113200288000010320000800003024000432002164000102080000320000208000432001518000032000010
400024160046400031113200208000010320000800003024000532001844000102080000320000208000032000018000032000010
400024160046400031113200208000010320000800003024000532001844000102080000320000208000032000018000032000010
400024160046400031113200208000010320000800003024000532001844000102080000320000208000032000018000032000010
400025160100400081113200548001610320066800003024000532001844000102080000320000208000032000018000032000010