Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (1D)

Test 1: uops

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660053226060551405020044008200060003054060002000400020008000120004000
660043179860051400420004000200060003054060002000400020008000120004000
660043179860051400420004000200060003054060002000400020008000120004000
660043200460091400820004000200060263059260002000400020008000120004000
660053232660091400820004000200060003055260002000400020008000120004000
660043186460051400420004000200060003054060002000400020008000120004000
660043187860051400420004000200060003054060002000400020008000120004000
660043180560051400420004000200060003054060002000400020008000120004000
660043187160051400420004000200060003054060002000400020008000120004000
660043186760051400420004000200060003054260002000400020008000120004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020416005448013510132002816000610032001016000830048007832004504801182001600083200142001600086400281160000320000100
48020416006148014310132003616000610032001216000830048002632004504801182001600083200142001600086400281160000320000100
48020416004848013110132002416000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020516008548019910132006616003210032006616000830048039832005004801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048003432002944801182001600083200142001600086400281160000320000100
48020416004848013110132002416000610032001016000830048003432002944801182001600083200142001600086400281160000320000100
48020416004848013110132002416000610032001016000830048003432002944801182001600083200142001600086400281160000320000100
48020516008548019910132006616003210032006616000830048002632004504801182001600083200142001600086400281160000320000100
48020416004848013110132002416000610032001016000830048005632004544801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048003432002944801182001600083200142001600366401401160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516054548013311320100160022103200381600083048002432003984800282016000832001420160000640000116000032000010
48002416005248003911320028160000103200001600003048006032003364800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600003048001232003364800102016000032000020160000640000116000032000010
48002416004748003311320022160000103200001600003048000632003364800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600363048010823971744801122016003632007020160036640140116000032000010
48002416004648003111320020160000103200001600003048000032003364800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600003048000032003364800102016000032000020160000640000116000032000010
48002416005448004511320028160006103200101600003048001024642324800102016000032000020160000640000116000032000010
48002516008348010311320060160032103200661601123048318427234824803462016011232022420160000640000116000032000010
48002416004648003111320020160000103200001600003048000032003364800102016000032000020160060640232116000032000010