Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (2D)

Test 1: uops

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660052999060551405020044008200060003054060002000400020008000120004000
660042975360091400820004000200060003054060002000400020008000120004000
660042973760051400420004000200060003054060002000400020008000120004000
660042974660051400420004000200060003054060002000400020008000120004000
660042981860051400420004000200060003054060002000400020008000120004000
660042973860051400420004000200060003054060002000400020008000120004000
660042991360091400820004000200060003054060002000400020008000120004000
660042986660051400420004000200060003054060002000400020008000120004000
660042996060051400420004000200060003054060002000400020008000120004000
660043021560051400420004000200060003054060002000400020008000120004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020516015848021510132009216002210032003616000830048002422660124801202001600083200142001600086400281160000320000100
48020416005948014310132003616000610032001216000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016009230048189230529364803662001600923201822001600086400281160000320000100
48020416006248014310132003616000610032001216000830048006832004544801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600366401401160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016003630048135431843844802002001600363200702001600086400281160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516016648012511320092160022103200361601203048335828600544803662016012032023820160000640000116000032000010
48002416005248003911320028160000103200001601123048318631662144803462016011232022420160000640000116000032000010
48002416005248003911320028160000103200001600003048000032003364800102016000032000020160000640000116000032000010
48002516009348010511320062160032103200661600283048092231972904800942016002832005620160000640000116000032000010
48002416005248003911320028160000103200001600003048002032003364800102016000032000020160000640000116000032000010
48002416005248003911320028160000103200001600003048000032003364800102016000032000020160000640000116000032000010
48002416044048035111320228160112103202241600363048031832011844801102016003632007020160000640000116000032000010
48002416005248003911320028160000103200001600003048000032003624800102016000032000020160000640000116000032000010
48002516011248011311320070160032103200661600003048031226414224800102016000032000020160112640448116000032000010
48002516010148011311320070160032103200661600003048000032003364800102016000032000020160000640000116000032000010