Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (2S)

Test 1: uops

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052977850531405010024008100030003057650001000400010004000110004000
650042953250091400810004000100030003057650001000400010004000110004000
650042952550091400810004000100030003057650001000400010004000110004000
650042978550091400810004000100030003057650001000400010004000110004000
650042952650091400810004000100030003057650001000400010004000110004000
650043048050091400810004000100030003056850001000400010004000110004000
650043003950091400810004000100030003057650001000400010004000110004000
650042998150091400810004000100030003056850001000400010004000110004000
650042955450091400810004000100030003056850001000400010004000110004000
650042977550091400810004000100030003056850001000400010004000110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160176400208101320096800111003200398000430024001224116224001172008000432001520080004320015180000320000100
400204160053400132101320028800031003200128000430024001732002644001162008000432001520080018320071180000320000100
400204160046400124101320020800031003200128000430024001732002644001162008000432001520080004320015180000320000100
400204160046400124101320020800031003200128000430024001732002644001162008000432001520080004320015180000320000100
400204160046400124101320020800031003200128000430024001732002644001162008000432001520080004320015180000320000100
400204160046400124101320020800031003200128001830024006531447524001852008001832007120080004320015180000320000100
400204160067400136101320032800031003200138000430024032532003604001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128000430024002232002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128000430024001632002964001162008000432001520080018320071180000320000100
400204160060400130101320026800031003200138000430024001632002964001162008000432001520080018320071180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160292400118113200968001110320039800043024001227364584000272080004320015208000032000018000032000010
400024160054400039113200288000010320000800003024012532004064000102080000320000208000032000018000032000010
400025160084400093113200668001610320067800003024012225763724000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000832003724000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800183024005326168204000952080018320071208000032000018000032000010
400024160048400035113200248000010320000800003024003832003724000102080000320000208003132012318000032000010
400024160055400039113200288000010320000800003024000232003724000102080000320000208000032000018000032000010