Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (4H)

Test 1: uops

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052970850511404810024008100030003057650001000400010004000110004000
650042953550091400810004000100030003054850001000400010004000110004000
650042951350051400410004000100030003054850001000400010004000110004000
650042951650051400410004000100030003054850001000400010004000110004000
650042954450051400410004000100030003054850001000400010004000110004000
650042951350051400410004000100030003054850001000400010004000110004000
650042951450051400410004000100030003054850001000400010004000110004000
650042951450051400410004000100030003054850001000400010004000110004000
650042951350051400410004000100030003054850001000400010004000110004000
650042951550051400410004000100030003054850001000400010004000110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160534400208101320096800111003200398001630024004624832054001742008001632006220080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001432004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024002532004604001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400205160097400179101320062800161003200668000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160149400110113200888001110320038800173024005525832314000892080017320066208000432001518000032000010
400025160108400100113200768001310320057800003024001827929874000102080000320000208000032000018000032000010
400024160046400031113200208000010320000800003024000532001844000102080000320000208000032000018000032000010
400024160046400031113200208000010320000800003024000532001844000102080000320000208001832007118000032000010
400025160082400089113200628001610320067800183024028530569784000952080018320071208000432001518000032000010
400024160050400037113200268000010320000800003024000432002164000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000432002164000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800003024000432002164000102080000320000208000032000018000032000010
400024160048400035113200248000010320000800183024050628758114000942080018320071208000032000018000032000010
400024160048400035113200248000010320000800003024001332002164000102080000320000208000032000018000032000010