Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (8B)

Test 1: uops

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052974350511404810024008100030003057650001000400010004000110004000
650042959350091400810004000100030003054850001000400010004000110004000
650042954350051400410004000100030003054850001000400010004000110004000
650042954150051400410004000100030003054850001000400010004000110004000
650042984450051400410004000100030003054850001000400010004000110004000
650042954850051400410004000100030003054850001000400010004000110004000
650042956750051400410004000100030003054850001000400010004000110004000
650042953250051400410004000100030003054850001000400010004000110004000
650042955150051400410004000100030003057650001000400010004000110004000
650043026150211402010004000100030003054050001000400010004000110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160162400208101320096800111003200398002830024046126042434002312008002832010920080004320015180000320000100
400204160061400140101320036800031003200138000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128001830024047331940434001842008001832007120080004320015180000320000100
400204160054400132101320028800031003200128000430024001532004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128001830024005324117884001852008001832007120080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400205160097400179101320062800161003200668000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100
400205160090400187101320070800161003200678000430024001232004524001162008000432001520080004320015180000320000100
400204160054400132101320028800031003200128000430024001232004524001162008000432001520080004320015180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160164400118113200968001110320039800003024010132003444000102080000320000208000032000018000032000010
400024160052400039113200288000010320000800003024000032003364000102080000320000208000032000018000032000010
400024160052400039113200288000010320000800043024001232004524000262080004320015208000432001518000032000010
400024160061400050113200368000310320013800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208001432005618000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800143024039628889614000782080014320056208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800183024005325796444000952080018320071208000032000018000032000010