Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (8H)

Test 1: uops

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052969250531405010024008100030003057650001000400010004000110004000
650042977450091400810004000100030003058450001000400010004000110004000
650042991450091400810004000100030003058450001000400010004000110004000
650042974750091400810004000100030003057650001000400010004000110004000
650042986050091400810004000100030013059650001000400010004000110004000
650042999350091400810004000100030003058050001000400010004000110004000
650043034050091400810004000100030003057650001000400010004000110004000
650042951550091400810004000100030003057650001000400010004000110004000
650042951550091400810004000100030003057650001000400010004000110004000
650042950950091400810004000100030003057650001000400010004000110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160162400208101320096800111003200398000430024001624179024001172008000432001520080004320015180000320000100
400205160095400175101320058800161003200668000430024002232003224001162008000432001520080004320015180000320000100
400204160049400128101320024800031003200128000430024001632002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128000430024003132002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128001830024008730983204001852008001832007120080004320015180000320000100
400205160098400172101320058800131003200578000430024002332002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128000430024001632002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128001830024005731307124001852008001832007120080004320015180000320000100
400205160092400172101320058800131003200548000430024001632002964001162008000432001520080004320015180000320000100
400204160048400128101320024800031003200128000430024001632002964001162008000432001520080004320015180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160160400118113200968001110320039800043024001232004524000262080004320015208000432001518000032000010
400024160054400039113200288000010320000800183024051531901864000942080018320071208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400025160117400089113200628001610320066800003024000032003724000102080000320000208000432001518000032000010
400024160064400044113200308000310320013800003024000432003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400024160054400039113200288000010320000800003024000032003724000102080000320000208000032000018000032000010
400025160090400097113200708001610320067800003024000032003724000102080000320000208000032000018000032000010
400025160100400089113200628001610320066800003024000032003724000102080000320000208000032000018000032000010