Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (post-index, 16B)

Test 1: uops

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005297206053100340481002100240081000300030333070860001000400020004000100110004000
65004296246009100140081000100040001000300030003057660001000400020004000100110004000
65004295186009100140081000100040001000300030003057660001000400020004000100110004000
65004295036009100140081000100040001000300030003057660001000400020004000100110004000
65004294926009100140081000100040001000300030003057660001000400020004000100110004000
65004294936009100140081000100040001000300030003057660001000400020004000100110004000
65004294956009100140081000100040001000300030003057660001000400020004000100110004000
65004294956009100140081000100040001000300030003057660001000400020004000100110004000
65004294996009100140081000100040001000300030003057660001000400020004000100110004000
65004294936009100140081000100040001000300030003057660001000400020004000100110004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160326480219801123200968001180112320039800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800162403462400462602467480190200800163200622001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400205160089480203801173200708001680118320067800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400204160052480135801043200288000380104320012800042403122400123200416480120200800043200152001600083200158000480000320000100
400205160089480203801173200708001680118320067800042403122400123200416480120200800043200152001600083200158000480000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160166480129800223200968001180022320039800042400422400123201570480030208000432001520160036320071800178000032000010
400024160052480045800143200288000380014320012800002400302400003200336480010208000032000020160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400003200336480010208000032000020160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400003200336480010208000032000020160000320000800018000032000010
400025160104480105800273200628001680028320066800182400832400722765712480113208001832007120160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400003200336480010208000032000020160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400003200336480010208000032000020160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400003200336480010208000032000020160000320000800018000032000010
400025160089480113800273200708001680028320067800002400302400863200340480010208000032000020160000320000800018000032000010
400024160052480039800113200288000080010320000800002400302400303200336480010208000032000020160028320056800158000032000010