Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4R (post-index, 1D)

Test 1: uops

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
66005297747057100340502004100240082000300060003057670002000400030008000100120004000
66004298007009100140082000100040002000300060003057670002000400030008000100120004000
66004300017009100140082000100040002000300060003057670002000400030008000100120004000
66004295707009100140082000100040002000300060003057670002000400030008000100120004000
66004295517009100140082000100040002000300060003057670002000400030008000100120004000
66004295457009100140082000100040002000300060003057670002000400030008000100120004000
66004295557009100140082000100040002000300060003057670002000400030008000100120004000
66004295777009100140082000100040002000300060003057670002000400030008000100120004000
66004295557009100140082000100040002000300060003057670002000400030008000100120004000
66004295667009100140082000100040002000300060003057670002000400030008000100120004000

Test 2: throughput

Count: 8

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4802051601515602268011232009216002280112320036160008240312480024227561256012420016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802051600935602308011832007816003480118320068160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024005464014080018160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160008240312480036320024656012220016000832001420024001264002880004160000320000100
4802041600465601308010432002016000680104320010160036240354480120289978656022220016003632007020024001264002880004160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4800251601785601448002232010016002280022320038160008240042480034320029456003220160008320014202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160036240084480118304948256013220160036320070202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160028240072481222320108856010820160028320056202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010
4800241600485600358001132002416000080010320000160000240030480010320023256001020160000320000202400006400008000116000032000010