Icestorm: LD4R (post-index, 2D) measurements

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.004

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66005	29729	7057	1003	4050	2004	1002	4008	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29550	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29563	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29539	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29550	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29551	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29587	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29988	7005	1001	4004	2000	1000	4000	2000	3000	6002	30552	7000	2000	4000	3000	8000	1001	2000	4000
66004	29831	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000
66004	29537	7005	1001	4004	2000	1000	4000	2000	3000	6000	30548	7000	2000	4000	3000	8000	1001	2000	4000

Count: 8

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480205	160297	560226	80112	320092	160022	80112	320036	160008	240312	480026	2285264	560124	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160063	560146	80104	320036	160006	80104	320012	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240054	640140	80018	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160054	560138	80104	320028	160006	80104	320010	160008	240312	480026	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480025	160177	560144	80022	320100	160022	80022	320038	160008	240042	480068	2604900	560034	20	160008	320014	20	240012	640028	80004	160000	320000	10
480024	160060	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560048	80014	320028	160006	80014	320010	160000	240030	480010	3200232	560010	20	160000	320000	20	240054	640140	80018	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160036	240084	480120	3091462	560132	20	160036	320070	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480010	3200232	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10

LD4R (post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations