Icestorm: LD4R (post-index, 4S) measurements

Code:

  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
65005	29715	6055	1003	4050	1002	1002	4008	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29484	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29472	6005	1001	4004	1000	1000	4000	1001	3003	3003	30580	6006	1001	4004	2000	4000	1001	1000	4000
65004	29483	6005	1001	4004	1000	1000	4000	1000	3000	3020	30656	6000	1000	4000	2000	4000	1001	1000	4000
65004	29490	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29485	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29486	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29481	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29505	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000
65004	29497	6005	1001	4004	1000	1000	4000	1000	3000	3000	30548	6000	1000	4000	2000	4000	1001	1000	4000

Count: 8

Code:

  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400205	160316	480219	80112	320096	80011	80112	320039	80004	240312	240012	2443658	480121	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80018	240353	240053	2588492	480203	200	80018	320071	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320012	80004	240312	240012	3200452	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400026	160199	480193	80035	320134	80024	80036	320092	80004	240042	240012	3200452	480030	20	80004	320015	20	160008	320015	80004	80000	320000	10
400024	160062	480053	80014	320036	80003	80014	320013	80000	240030	240000	3200372	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160054	480039	80011	320028	80000	80010	320000	80000	240030	240000	3200372	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160054	480039	80011	320028	80000	80010	320000	80000	240030	240000	3200372	480010	20	80000	320000	20	160008	320015	80004	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160036	320071	80017	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160068	480039	80011	320028	80000	80010	320000	80000	240030	240016	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10

LD4R (post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations