Icestorm: LD4R (post-index, 8B) measurements

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
65005	29986	6053	1003	4048	1002	1002	4008	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29580	6009	1001	4008	1000	1000	4000	1000	3000	3000	30540	6000	1000	4000	2000	4000	1001	1000	4000
65004	29520	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29548	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29527	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29525	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29523	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29517	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29521	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000
65004	29525	6009	1001	4008	1000	1000	4000	1000	3000	3000	30568	6000	1000	4000	2000	4000	1001	1000	4000

Count: 8

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400205	160290	480219	80112	320096	80011	80112	320039	80004	240312	240012	2414822	480121	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160054	480135	80104	320028	80003	80104	320013	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160036	320071	80017	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80018	240353	240058	3123168	480203	200	80018	320071	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100
400204	160046	480127	80104	320020	80003	80104	320012	80004	240312	240017	3200264	480120	200	80004	320015	200	160008	320015	80004	80000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400025	160171	480129	80022	320096	80011	80022	320039	80018	240083	240420	2869687	480112	20	80018	320071	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400025	160083	480105	80027	320062	80016	80028	320067	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160036	320071	80017	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10
400024	160046	480031	80011	320020	80000	80010	320000	80000	240030	240005	3200184	480010	20	80000	320000	20	160000	320000	80001	80000	320000	10

LD4R (post-index, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations