Icestorm: LD4 (multiple, 16B) measurements

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.012

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	30437	12079	1	8070	4008	8016	4000	12035	59488	12000	4000	8000	4000	20000	1	4000	8000
72004	30606	12013	1	8012	4000	8000	4000	12010	59156	12000	4000	8000	4000	20000	1	4000	8000
72004	30463	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	30496	12013	1	8012	4000	8000	4000	12000	59160	12000	4000	8000	4000	20000	1	4000	8000
72004	30374	12013	1	8012	4000	8000	4000	12006	59148	12000	4000	8000	4000	20000	1	4000	8000
72004	30064	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	30058	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	30068	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	30019	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72005	30168	12019	1	8018	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000

Count: 8

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320172	960207	101	640084	320022	100	640036	320034	300	960120	3942944	960190	200	320034	640066	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960050	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960056	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960062	6400242	960118	200	320008	640016	200	320036	1600180	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960036	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960052	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320047	960127	101	640020	320006	100	640010	320008	300	960056	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320082	960191	101	640056	320034	100	640064	320008	300	960164	6400246	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960064	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320046	960125	101	640018	320006	100	640010	320008	300	960036	6400242	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320157	960119	11	640086	320022	10	640036	320034	30	960110	4864724	960100	20	320034	640066	20	320008	1600040	1	320000	640000	10
960025	320106	960119	11	640074	320034	10	640064	320000	30	960100	6400232	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320036	30	960108	4883236	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320000	30	960034	6400232	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320064	30	960648	4944922	960192	20	320064	640128	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320000	30	960000	6400232	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320036	30	960108	4033988	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320048	960031	11	640020	320000	10	640000	320000	30	960000	6400232	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320071	960045	11	640028	320006	10	640010	320000	30	960060	6400180	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320046	960029	11	640018	320000	10	640000	320000	30	960012	6400180	960010	20	320000	640000	20	320062	1600304	1	320000	640000	10

LD4 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations