Icestorm: LD4 (multiple, 2D) measurements

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.006

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72006	35303	12079	1	8070	4008	8016	4000	12076	59316	12000	4000	8000	4002	20008	1	4000	8000
72005	30439	12019	1	8014	4004	8008	4000	12082	59268	12000	4000	8000	4004	20020	1	4000	8000
72004	30409	12007	1	8006	4000	8000	4004	12012	59140	12012	4004	8008	4000	20000	1	4000	8000
72004	30143	12007	1	8006	4000	8000	4000	12000	59080	12000	4000	8000	4000	20000	1	4000	8000
72004	30246	12007	1	8006	4000	8000	4008	12178	59494	12020	4008	8012	4001	20000	1	4000	8000
72004	30099	12007	1	8006	4000	8000	4000	12000	59080	12000	4000	8000	4000	20000	1	4000	8000
72004	30298	12007	1	8006	4000	8000	4000	12000	59080	12000	4000	8000	4000	20000	1	4000	8000
72004	30033	12007	1	8006	4000	8000	4000	12000	59080	12000	4000	8000	4000	20000	1	4000	8000
72004	30011	12007	1	8006	4000	8000	4000	12000	59080	12000	4000	8000	4000	20000	1	4000	8000
72004	30967	12007	1	8006	4000	8000	4000	12000	59112	12000	4000	8000	4000	20000	1	4000	8000

Count: 8

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960206	320209	960267	101	640120	320046	100	640082	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320058	960139	101	640032	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320096	960197	101	640062	320034	100	640064	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320088	960201	101	640066	320034	100	640064	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320088	960201	101	640066	320034	100	640064	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320036	1600180	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320093	960197	101	640062	320034	100	640064	320008	300	960118	6400390	960118	200	320008	640016	200	320036	1600180	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320155	960115	11	640082	320022	10	640036	320036	30	960120	6176976	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320000	30	960012	6400388	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320036	30	960120	5594000	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320028	30	961284	5865084	960092	20	320028	640056	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320036	30	960496	5610872	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320000	30	960012	6400388	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320036	30	961134	5870478	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320000	30	960012	6400388	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320028	30	960104	4081278	960092	20	320028	640056	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320000	30	960036	6400388	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10

LD4 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations