Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (multiple, 2S)

Test 1: uops

Code:

  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660052995460551405020044008200060003056860002000400020008000120004000
660042991660091400820004000200060003054060002000400020008000120004000
660042975660051400420004000200060003054060002000400020008000120004000
660042985260051400420004000200060003054060002000400020008000120004000
660042974960051400420004000200060003054060002000400020008000120004000
660042972660051400420004000200060023054460002000400020008000120004000
660042971360051400420004000200060003054460002000400020028008120004000
660042996560051400420004000200060003054060002000400020008000120004000
660042970260051400420004000200060003054060002000400020008000120004000
660042973860051400420004000200060003054060002000400020008000120004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020516017048022310132010016002210032003816000830048005828186404801202001600083200142001600086400281160000320000100
48020416006148014310132003616000610032001216000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600366401401160000320000100
48020416005448013510132002816000610032001016000830048003624094604801202001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048003832004504801182001600083200142001600086400281160000320000100
48020516010048019510132006216003210032006416003430048032225608324801962001600343200662001600086400281160000320000100
48020416005448013510132002816000610032001016000830048005032004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016003630048118631835304802002001600363200702001600086400281160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516016848013311320100160022103200381600083048003624642604800302016000832001420160032640120116000032000010
48002416004648003111320020160000103200001600003048005432001844800102016000032000020160000640000116000032000010
48002516008348010511320062160032103200661600003048013832001844800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600003048004832001844800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600003048001232001844800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600003048001232001844800102016000032000020160036640140116000032000010
48002416005348003111320020160000103200001600003048017632001884800102016000032000020160000640000116000032000010
48002416004648003111320020160000103200001600283048064632008264800922016002832005620160000640000116000032000010
48002416004648003111320020160000103200001600003048001232001844800102016000032000020160008640028116000032000010
48002416004848003511320024160000103200001600003048005032001844800102016000032000020160028640112116000032000010