Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (multiple, 4H)

Test 1: uops

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.008

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660052979060551405020044008200060003057660002000400020008000120004000
660042959860091400820004000200060003057660002000400020008000120004000
660042977360091400820004000200060003057660002000400020008000120004000
660042957260091400820004000200060003057660002000400020008000120004000
660042954360091400820004000200060003057660002000400020008000120004000
660042963460091400820004000200060003057660002000400020008000120004000
660042987860091400820004000200060003057660002000400020008000120004000
660042955460091400820004000200060003057660002000400020008000120004000
660042955460091400820004000200060003057660002000400020008000120004000
660042954960091400820004000200060003057660002000400020008000120004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020516015748021510132009216002210032003616000830048002622660644801202001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002628196644801202001600083200142001600366401401160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016003630048011029020344802022001600363200702001600086400281160000320000100
48020516009148020310132007016003210032006616000830048032032004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048002632004504801182001600083200142001600086400281160000320000100
48020416005448013510132002816000610032001016000830048006232004504801182001600083200142001600086400281160000320000100
48020516009148020310132007016003210032006616000830048005232004504801182001600083200142001600086400281160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516017848013311320100160022103200381600003048000224643884800102016000032000020160000640000116000032000010
48002516008548010911320066160032103200661600003048000232003884800102016000032000020160000640000116000032000010
48002416004848003511320024160000103200001600003048001032002324800102016000032000020160036640140116000032000010
48002416005948003711320026160000103200001600003048001032002324800102016000032000020160000640000116000032000010
48002416004948003711320026160000103200001600003048006432002364800102016000032000020160000640000116000032000010
48002516008748009511320058160026103200541600003048003232003884800102016000032000020160000640000116000032000010
48002516009348010111320058160032103200641600003048002032003884800102016000032000020160000640000116000032000010
48002416004848003511320024160000103200001600003048001032002324800102016000032000020160064640252116000032000010
48002416014448007111320054160006103200121600083048004426564644800302016000832001420160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010