Icestorm: LD4 (multiple, 4S) measurements

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.012

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	30348	12081	1	8072	4008	0	8016	4000	12000	59152	12000	4000	8000	4000	20000	1	4000	8000
72004	30013	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29975	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29978	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29979	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72005	29984	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	30214	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29973	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29968	12013	1	8012	4000	0	8000	4000	12027	59204	12000	4000	8000	4000	20000	1	4000	8000
72004	29979	12013	1	8012	4000	0	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000

Count: 8

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960206	320213	960263	101	640116	320046	100	640082	320008	300	960036	5376402	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960066	6400476	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320054	960133	101	640026	320006	100	640010	320008	300	960064	6400476	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320054	960129	101	640022	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320036	1600180	1	320000	640000	100
884657	311131	884818	2238	587651	294929	2135	587640	320008	300	960078	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960064	6400390	960118	200	320008	640016	200	320036	1600180	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320149	960115	11	640082	320022	10	640036	320036	30	960120	4285028	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320036	30	961596	5859178	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320604	960507	11	640328	320168	10	640336	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960025	320088	960111	11	640066	320034	10	640064	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960045	11	640028	320006	10	640010	320000	30	960024	4864438	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320064	30	961170	5883398	960192	20	320064	640128	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320036	30	960416	5497850	960110	20	320036	640072	20	320008	1600040	1	320000	640000	10
960025	320106	960107	11	640062	320034	10	640064	320000	30	960012	6400388	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320054	960039	11	640028	320000	10	640000	320000	30	960168	6400400	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10

LD4 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations