Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (multiple, 8B)

Test 1: uops

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.008

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6600530580605314048200404008200060003057260002000400020008000120004000
6600429942600914008200004000200060003056860002000400020008000120004000
6600430134600914008200004000200060043057660002000400020008000120004000
6600429973600914008200004000200060003056860002000400020008000120004000
6600429764600914008200004000200060003056860002000400020008000120004000
6600429743600914008200004000200060003056860002000400020008000120004000
6600429758600914008200004000200060003056860002000400020008000120004000
6600429754600914008200004000200060003056860002000400020008000120004000
6600429745600914008200004000200060203061260002000400020008000120004000
6600530140601314012200004000200060003057660002000400020008000120004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020516014948021510132009216002210032003616000830048002422660124801202001600083200142001600086400281160000320000100
48020416005948014310132003616000610032001216000830048002432003984801182001600083200142001600086400281160000320000100
48020416005948014310132003616000610032001216000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016003630048132828124784802002001600363200702001600086400281160000320000100
48020416005248013510132002816000610032001016000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016000830048002432003984801182001600083200142001600086400281160000320000100
48020516008948020310132007016003210032006616000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016000830048002432003984801182001600083200142001600086400281160000320000100
48020416005248013510132002816000610032001016000830048002432003984801182001600083200142001600086400281160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516017148013311320100160022103200381600363048011024206104801122016003632007020160008640028116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002516009148011311320070160032103200661600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160036640140116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010
48002416005448003911320028160000103200001600003048000232003884800102016000032000020160000640000116000032000010