Icestorm: LD4 (multiple, 8H) measurements

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.012

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	30228	12077	1	8068	4008	8016	4000	12000	59152	12000	4000	8000	4000	20000	1	4000	8000
72004	29927	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29925	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29967	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29925	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29933	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29921	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29921	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29966	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000
72004	29925	12013	1	8012	4000	8000	4000	12000	59136	12000	4000	8000	4000	20000	1	4000	8000

Count: 8

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320154	960197	101	640074	320022	100	640036	320034	300	960948	4469276	960190	200	320034	640066	200	320008	1600040	1	320000	640000	100
960204	320058	960139	101	640032	320006	100	640010	320008	300	960036	5376402	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960064	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320064	960131	101	640024	320006	100	640010	320008	300	960024	5376306	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320036	960111	101	640004	320006	100	640010	320008	300	960024	6400294	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320048	960127	101	640020	320006	100	640010	320008	300	960024	6400294	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960205	320097	960189	101	640054	320034	100	640064	320008	300	960160	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100
960204	320052	960135	101	640028	320006	100	640010	320008	300	960036	6400390	960118	200	320008	640016	200	320008	1600040	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320173	960119	11	640086	320022	10	640036	320034	30	960110	4864664	960100	20	320034	640066	20	320008	1600040	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320000	30	960048	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320036	30	960120	5735108	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320060	960039	11	640028	320000	10	640000	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320064	30	960532	5186300	960190	20	320064	640128	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320036	30	961068	5875660	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320036	30	960120	4295028	960110	20	320036	640072	20	320000	1600000	1	320000	640000	10
960024	320052	960039	11	640028	320000	10	640000	320000	30	960012	6400328	960010	20	320000	640000	20	320000	1600000	1	320000	640000	10

LD4 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations