Icestorm: LD4 (multiple, post-index, 16B) measurements

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.012

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
72005	30165	13083	1003	8072	4008	1002	8016	4000	3000	12000	59152	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30554	13013	1001	8012	4000	1000	8000	4000	3000	12000	59144	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30762	13013	1001	8012	4000	1000	8000	4000	3000	12000	59136	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30398	13013	1001	8012	4000	1000	8000	4000	3000	12000	59144	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	29972	13013	1001	8012	4000	1000	8000	4000	3000	12000	59136	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	29945	13013	1001	8012	4000	1000	8000	4000	3000	12000	59136	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	29953	13013	1001	8012	4000	1000	8000	4000	3000	12000	59136	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30621	13013	1001	8012	4000	1000	8000	4000	3000	12000	59160	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30204	13013	1001	8012	4000	1000	8000	4000	3000	12000	59144	13000	4000	8000	0	5000	20000	1001	4000	8000	0
72004	30476	13013	1001	8012	4000	1000	8000	4000	3000	12000	59136	13000	4000	8000	0	5000	20000	1001	4000	8000	0

Count: 8

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320175	1040212	80106	640084	320022	80106	640036	320008	240306	960072	3927366	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960076	6400450	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960040	6402686	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960056	6400450	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960050	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320036	240327	960168	5098708	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960120	6400454	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960044	6400450	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960074	6400294	1040120	200	320008	640016	200	400570	1602280	80114	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320036	240327	960260	5988684	1040211	200	320036	640072	200	400150	1600600	80030	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320155	1040120	80016	640082	320022	80016	640036	320036	240057	961432	6355974	1040119	20	320036	640072	20	400010	1600040	80002	320000	640000	10
960024	320056	1040039	80011	640028	320000	80010	640000	320036	240057	960142	5709472	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320000	240030	960012	6400388	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10
960024	320060	1040039	80011	640028	320000	80010	640000	320036	240057	960120	5123328	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320000	240030	960058	6400388	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320036	240057	961286	5875700	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320000	240030	960012	6400388	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320036	240057	960120	4292288	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320000	240030	960012	6400388	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320036	240057	961258	5873900	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10

LD4 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations