Icestorm: LD4 (multiple, post-index, 2D) measurements

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.012

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	38008	13062	1002	8056	4004	1001	8008	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29982	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29942	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29944	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29931	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	30088	13013	1001	8012	4000	1000	8000	4000	3000	12004	59160	13000	4000	8000	5000	20000	1001	4000	8000
72004	30280	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29931	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29971	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29932	13013	1001	8012	4000	1000	8000	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000

Count: 8

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320171	1040210	80106	640082	320022	80106	640036	320008	240306	960072	4183970	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960064	6400294	1040120	200	320008	640016	200	400045	1600180	80009	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400080	1600320	80016	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400045	1600180	80009	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960048	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320053	1040130	80102	640022	320006	80102	640010	320008	240306	960036	6400242	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960205	320088	1040209	80109	640066	320034	80109	640066	320008	240306	960036	5273854	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320046	1040126	80102	640018	320006	80102	640010	320036	240327	961004	5887994	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320054	1040136	80102	640028	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
910220	328931	982155	83456	594493	304206	83109	594399	320008	240036	960038	4609112	1040030	20	320008	640016	20	400000	1600000	80001	320000	640000	10
960024	320054	1040039	80011	640028	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10
960025	320102	1040115	80019	640062	320034	80019	640066	320000	240030	960136	6400232	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10
960025	320100	1040135	80019	640082	320034	80019	640066	320036	240057	961508	6321282	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960032	6400232	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320048	1040031	80011	640020	320000	80010	640000	320000	240030	960000	6400232	1040010	20	320000	640000	20	400045	1600180	80009	320000	640000	10

LD4 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations