Icestorm: LD4 (multiple, post-index, 4H) measurements

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66005	29943	7057	1003	4050	2004	1002	4008	2000	3000	6010	30596	7000	2000	4000	3000	8000	1001	2000	4000
66005	29648	7020	1002	4016	2002	1001	4004	2000	3000	6000	30576	7000	2000	4000	3000	8000	1001	2000	4000
66157	31028	7189	1106	4016	2067	1102	4000	2000	3000	6000	30584	7000	2000	4000	3000	8000	1001	2000	4000
66004	30344	7009	1001	4008	2000	1000	4000	2000	3000	6000	30576	7000	2000	4000	3000	8000	1001	2000	4000
66004	30194	7009	1001	4008	2000	1000	4000	2000	3000	6002	30596	7000	2000	4000	3000	8000	1001	2000	4000
66004	30135	7009	1001	4008	2000	1000	4000	2000	3000	6000	30576	7000	2000	4000	3000	8000	1001	2000	4000
66004	29777	7009	1001	4008	2000	1000	4000	2000	3000	6000	30584	7000	2000	4000	3000	8000	1001	2000	4000
66004	29854	7009	1001	4008	2000	1000	4000	2000	3000	6000	30576	7000	2000	4000	3000	8000	1001	2000	4000
66004	30589	7009	1001	4008	2000	1000	4000	2000	3000	6000	30584	7000	2000	4000	3000	8000	1001	2000	4000
66004	29939	7009	1001	4008	2000	1000	4000	1792	2687	5382	27422	6270	1792	3584	3003	8008	1002	2000	4000

Count: 8

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480206	160229	560318	80126	320142	160050	80126	320094	160008	240312	480042	2349072	560124	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160055	560138	80104	320028	160006	80104	320012	160008	240312	480060	2914452	560124	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160008	240312	480036	3200246	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160008	240312	480036	3200246	560122	200	160008	320014	200	240054	640140	80018	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160008	240312	480048	3200246	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160036	240354	480120	2958458	560222	200	160036	320070	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	153310	230250	460406	3066600	536674	190	153310	306618	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160008	240312	480036	3200246	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160046	560130	80104	320020	160006	80104	320010	160008	240312	480024	3201074	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100
480204	160057	560132	80104	320022	160006	80104	320012	160008	240312	480044	3200450	560122	200	160008	320014	200	240012	640028	80004	160000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480025	160178	560144	80022	320100	160022	80022	320038	160008	240042	480026	2560464	560034	20	160008	320014	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480002	3200388	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160036	240084	480110	2982606	560132	20	160036	320070	20	240000	640000	80001	160000	320000	10
480025	160119	560140	80028	320078	160034	80028	320066	160000	240030	480034	3200388	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480002	3200388	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480025	160147	560160	80028	320098	160034	80028	320068	160000	240030	480008	3200466	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480014	3200388	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160036	240084	480118	2584486	560132	20	160036	320070	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160036	240084	480168	2620470	560132	20	160036	320070	20	240000	640000	80001	160000	320000	10
480024	160054	560039	80011	320028	160000	80010	320000	160000	240030	480002	3200388	560010	20	160000	320000	20	240000	640000	80001	160000	320000	10

LD4 (multiple, post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations