Icestorm: LD4 (multiple, post-index, 4S) measurements

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.006

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	30281	13085	1003	8074	4008	1002	8016	4000	3000	12000	59152	13000	4000	8000	5000	20000	1001	4000	8000
72004	29997	13013	1001	8012	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30031	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30025	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30018	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	29995	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30028	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30026	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	29965	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000
72004	30028	13007	1001	8006	4000	1000	8000	4000	3000	12000	59096	13000	4000	8000	5000	20000	1001	4000	8000

Count: 8

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320159	1040210	80106	640082	320022	80106	640036	320008	240306	960062	4094126	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320036	240327	960120	6325892	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320008	240306	960036	6400390	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320036	240327	961060	6365368	1040211	200	320036	640072	200	400045	1600180	80009	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320008	240306	960064	6400390	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320036	240327	960134	5428548	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320008	240306	960036	6400390	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320036	240327	960962	5867706	1040211	200	320036	640072	200	400045	1600180	80009	320000	640000	100
960204	320052	1040136	80102	640028	320006	80102	640010	320008	240306	960036	6400390	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320059	1040140	80102	640032	320006	80102	640010	320008	240306	960036	6400390	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320405	1040124	80016	640086	320022	80016	640036	320112	240114	963254	5694728	1040374	20	320112	640224	20	400420	1601680	80085	320000	640000	10
960024	320052	1040039	80011	640028	320000	80010	640000	320036	240057	960532	6401242	1040121	20	320036	640072	20	400010	1600040	80002	320000	640000	10
960024	320053	1040029	80011	640018	320000	80010	640000	320000	240030	960012	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320000	240030	960012	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320036	240057	960120	4801328	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320000	240030	960012	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320000	240030	960012	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320000	240030	960052	6400180	1040010	20	320000	640000	20	400080	1600320	80016	320000	640000	10
955589	319905	1035553	79739	637154	318660	79754	637152	320000	240030	960184	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320046	1040029	80011	640018	320000	80010	640000	320000	240030	960042	6400180	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10

LD4 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations