Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (multiple, post-index, 8B)

Test 1: uops

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
66005299017057100340502004100240082000300060003056870002000400030008000100120004000
66004295847009100140082000100040002000300060003056870002000400030008000100120004000
66004295897009100140082000100040002000300060253063670002000400030008000100120004000
66004299437009100140082000100040002000300060003057270002000400030008000100120004000
66004296957009100140082000100040002000300060003056870002000400030008000100120004000
66004295797009100140082000100040002000300060003056870002000400030008000100120004000
66004295777009100140082000100040002000300060003056870002000400030008000100120004000
66004295767009100140082000100040002000300060003056870002000400030008000100120004000
66004295787009100140082000100040002000300060063058070002000400030008000100120004000
66004297907009100140082000100040002000300060003056870002000400030008000100120004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4802051601775602288011232009416002280112320038160008240312480064252387656012420016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420224005464014080019160000320000100
4802051601115602508011832009816003480118320066160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024005464014080018160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100
4802041600545601388010432002816000680104320010160008240312480026320045056012220016000832001420024001264002880004160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4800251601515601368002232009216002280022320036160008240042480024275241256003420160008320014202400006400008000116000032000010
4800241600525600398001132002816000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480012320018456001020160000320000202400006400008000116000032000010
4800261601645602548004232015016006280042320122160000240030480012320018456001020160000320000202400006400008000116000032000010
4800241600465600318001132002016000080010320000160000240030480018320018456001020160000320000202400006400008000116000032000010