Icestorm: LD4 (multiple, post-index, 8H) measurements

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.006

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72005	32593	13081	1003	8070	4008	1002	8016	4000	3000	12000	59088	13000	4000	8000	5000	20000	1001	4000	8000
72004	30336	13007	1001	8006	4000	1000	8000	4000	3000	12000	59104	13000	4000	8000	5000	20000	1001	4000	8000
72004	30169	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29924	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000
72004	29923	13007	1001	8006	4000	1000	8000	4000	3000	12000	59080	13000	4000	8000	5000	20000	1001	4000	8000

Count: 8

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960205	320164	1040214	80106	640086	320022	80106	640036	320008	240306	960036	3968462	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320062	1040140	80102	640032	320006	80102	640010	320036	240327	960120	6400884	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320036	240327	960120	6400896	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960024	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320036	240327	961514	6401168	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960204	320048	1040128	80102	640020	320006	80102	640010	320008	240306	960050	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960204	320243	1040314	80116	640136	320062	80116	640122	320036	240327	960418	6400900	1040211	200	320036	640072	200	400010	1600040	80002	320000	640000	100
960205	320097	1040219	80109	640076	320034	80109	640066	320008	240306	960060	6400294	1040120	200	320008	640016	200	400010	1600040	80002	320000	640000	100
960205	320095	1040219	80109	640076	320034	80109	640066	320008	240306	960024	6400294	1040120	200	320008	640016	200	400045	1600180	80009	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960025	320510	1040120	80016	640082	320022	80016	640036	320000	240030	960012	4608344	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960025	320093	1040127	80019	640074	320034	80019	640066	320000	240030	960012	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320052	1040039	80011	640028	320000	80010	640000	320000	240030	960028	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960025	320105	1040129	80019	640076	320034	80019	640066	320000	240030	960012	5120344	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320052	1040039	80011	640028	320000	80010	640000	320000	240030	960012	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960025	320106	1040129	80019	640076	320034	80019	640066	320036	240057	960120	6192196	1040121	20	320036	640072	20	400000	1600000	80001	320000	640000	10
960024	320052	1040039	80011	640028	320000	80010	640000	320000	240030	960028	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960026	320138	1040200	80026	640112	320062	80026	640122	320000	240030	960012	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960024	320052	1040039	80011	640028	320000	80010	640000	320000	240030	960012	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10
960025	320107	1040125	80019	640072	320034	80019	640066	320000	240030	960012	6400328	1040010	20	320000	640000	20	400000	1600000	80001	320000	640000	10

LD4 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations