Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, B)

Test 1: uops

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650062992350301402610034012100030003056850001000400010008000110004000
650042973850091400810004000100030003056850001000400010008000110004000
650042966150091400810004000100030003056850001000400010008000110004000
650042965850091400810004000100030003056850001000400010008000110004000
650042965950091400810004000100030003056850001000400010008000110004000
650042965750091400810004000100030003056850001000400010008000110004000
650042966050091400810004000100030003056850001000400010008000110004000
650042965950091400810004000100030003056850001000400010008000110004000
650042965850091400810004000100030003056850001000400010008000110004000
650042969050091400810004000100030003056850001000400010008000110004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400206160218400191101320066800241003200928001830024034530327514001832008001832007020080004640030180000320000100
400204160065400116101320012800031003200128001830024044431882534001842008001832007120080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080018640142180000320000100
400204160053400116101320012800031003200128000430024001532004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160161400054113200328001110320038800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800183024005331077994000952080018320071208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000707842721249027011463539221870784283134208003264025418000032000010
400024160253400149113201098002910320115800293024068730356364001542080029320115208002864022418000032000010
400024160054400023113200128000010320000800433024101324640694002242080043320171208015664124418000032000010
400024160502400276113202068005910320233800003024000032003764000102080000320000208002664020818000032000010
400024160054400023113200128000010320000800003024001132003804000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024001732003884000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024000732003764000102080000320000208000064000018000032000010