Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, D)

Test 1: uops

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
660052988060331402820044008200060003057660002000400002000120001200040000
660042962160091400820004000200060003054860002000400002000120001200040000
660042959260051400420004000200060003054860002000400002000120001200040000
660042960860051400420004000200060003054860002000400002000120001200040000
660042960060051400420004000200060003054860002000400002000120001200040000
660042958360051400420004000200060003054860002000400002000120001200040000
660042960960051400420004000200060003054860002000400002000120001200040000
660042960260051400420004000200060003057660002000400002000120001200040000
660043000860051400420004000200060103056860002000400002000120001200040000
660042967960051400420004000200060003054860002000400002000120001200040000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020616055648022510132007616004810032009216003230048017222935004801882001600323200602001600369602041160000320000100
48020416005348011910132001216000610032001016000830048003628194644801202001600083200142001600089600421160000320000100
48020416004648011310132000616000610032001016000830048003632002504801182001600083200142001600089600421160000320000100
48020416004648011310132000616000610032001016000830048003632002504801182001600083200142001600369602101160000320000100
48020416006148012510132001816000610032001216000830048003423427084801202001600083200142001600089600421160000320000100
48020416004848011310132000616000610032001016000830048003432002944801182001600083200142001600089600421160000320000100
48020416004848011310132000616000610032001016000830048003432002944801182001600083200142001600089600421160000320000100
48020416004848011310132000616000610032001016003630048011831886704802022001600363200702001600089600421160000320000100
48020416004848011310132000616000610032001016000830048003432002944801182001600083200142001600089600421160000320000100
48020416004848011310132000616000610032001016000830048003432002944801182001600083200142001600089600421160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002516016148006911320036160022103200361600003048000224643884800102016000032000020160036960210116000032000010
48002416005448002311320012160000103200001600003048001032002324800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600003048001032002324800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600003048001032002324800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600363048011831722144801122016003632007020160000960000116000032000010
48002416004848001711320006160000103200001600003048001032002324800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600363048011828977744801122016003632007020160036960210116000032000010
48002416004848001711320006160000103200001600003048005232002324800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600003048014432003884800102016000032000020160000960000116000032000010
48002416004848001711320006160000103200001600003048001032002324800102016000032000020160000960000116000032000010