Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, H)

Test 1: uops

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650053069150311402810024008100030003056850001000400010008000110004000
650042980850091400810004000100030003056850001000400010008000110004000
650042977450091400810004000100030003056850001000400010008000110004000
650042977950091400810004000100030003056850001000400010008000110004000
650042977050091400810004000100030003059450001000400010008000110004000
650042965550091400810004000100030003056850001000400010008000110004000
650042980350091400810004000100030003056850001000400010008000110004000
650042972950091400810004000100030003056850001000400010008000110004000
650042971950091400810004000100030003056850001000400010008000110004000
650042994950091400810004000100030003056850001000400010008000110004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160179400146101320034800111003200398000430024001224820514001172008000432001520080004640030180000320000100
400204160064400117101320013800031003200138000430024002232004464001162008000432001520080004640030180000320000100
400205160090400168101320051800161003200678000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024003132004504001162008000432001520080004640030180000320000100
400204160074400121101320017800031003200138000430024001232004564001162008000432001520080004640030180000320000100
400204160054400116101320012800031003200128000430024029832006564001162008000432001520080004640030180000320000100
400204160054400116101320012800031003200128000430024001232004564001162008000432001520080004640030180000320000100
400205160101400163101320046800161003200668000430024001232004564001162008000432001520080004640030180000320000100
400204160054400116101320012800031003200128000430024001232004564001162008000432001520080004640030180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160183400059113200378001110320039800043024001227364514000272080004320015208000064000018000032000010
400024160046400017113200068000010320000800183024015031869964000942080018320071208000064000018000032000010
400024160046400017113200068000010320000800003024000532001884000102080000320000208000064000018000032000010
400024160046400017113200068000010320000800003024000532001884000102080000320000208000064000018000032000010
400024160046400017113200068000010320000800003024000532001884000102080000320000208000064000018000032000010
400024160046400017113200068000010320000800003024000932001884000102080000320000208000064000018000032000010
400024160046400017113200068000010320000800183024040328992754000942080018320071208000064000018000032000010
400024160111400026113200128000310320012800043024001232004464000262080004320015208000064000018000032000010
400024160046400017113200068000010320000800003024002932001884000102080000320000208000064000018000032000010
400024160046400017113200068000010320000800003024001232001924000102080000320000208001864014218000032000010