Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, S)

Test 1: uops

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650053060650291402610024008100030003057650001000400010008000110004000
650043041050091400810004000100030003054850001000400010008000110004000
650043050550051400410004000100030003054850001000400010008000110004000
650043022950051400410004000100030003055450001000400010008000110004000
650043007950051400410004000100030003054850001000400010008000110004000
650042965150051400410004000100030003054850001000400010008000110004000
650042969050051400410004000100030003054850001000400010008000110004000
650042967650051400410004000100030003054850001000400010008000110004000
650042966250051400410004000100130033056250051001400410008000110004000
650042966150051400410004000100030003054850001000400010008000110004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160177400149101320037800111003200398000430024001225940514001172008000432001520080004640030180000320000100
400205160090400168101320051800161003200678000430024001224260514001172008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400205160094400163101320046800161003200668000430024003232004464001162008000432001520080004640030180000320000100
400205160093400163101320046800161003200678000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001832004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080018640142180000320000100
400204160053400116101320012800031003200128000430024001232004464001162008000432001520080004640030180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160197400059113200378001110320039800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800183024005332010044000942080018320071208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024001432003764000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800003024006032004024000102080000320000208000064000018000032000010
400024160054400023113200128000010320000800143024042128931374000782080014320056208000064000018000032000010
400024160054400023113200128000010320000800003024000032003764000102080000320000208000064000018000032000010