Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, post-index, B)

Test 1: uops

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005297996031100340261002100240081001300330033058060061001400420008000100110004000
65004295636005100140041000100040001000300030003054860001000400020008000100110004000
65004295476005100140041000100040001000300030003054860001000400020008000100110004000
65004295346005100140041000100040001000300030003054860001000400020008000100110004000
65004295516005100140041000100040001000300030003054860001000400020008000100110004000
65004298366005100140041000100040001000300030003054860001000400020008000100110004000
65004298076005100140041000100040001000300030003054860001000400020008000100110004000
65004296806005100140041000100040001000300030013055260001000400020008000100110004000
65004298306009100140081000100040001000300030053056860001000400020008000100110004000
65004304026005100140041000100040001000300030003055260001000400020008000100110004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160159480155801123200328001180112320038800042403122400242622662480121200800043200152001600086400308000480000320000100
400204160078480123801043200168000380104320012800042403122400172427472480121200800043200152001600366401428001780000320000100
400204160053480119801043200128000380104320012800042403122400173200268480120200800043200152001600086400308000480000320000100
400204160046480113801043200068000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100
400205160091480173801173200408001680118320066800042403122400123200446480120200800043200152001600366401428001780000320000100
400204160053480119801043200128000380104320012800042403122400323200268480120200800043200152001600086400308000480000320000100
400204160046480113801043200068000380104320012800042403122400173200268480120200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600366401428001780000320000100
400204160046480113801043200068000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400173200268480120200800043200152001600366401428001780000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160522480065800223200328001180022320038800042400422400122656461480031208000432001520160008640030800048000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800182400832404803201416480112208001832007120160000640000800018000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400025160101480095800273200528001680028320066800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800002400302400003200376480010208000032000020160000640000800018000032000010
400024160054480023800113200128000080010320000800182400832404543201264480112208001832007120160008640030800048000032000010