Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, post-index, D)

Test 1: uops

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660042989470091001400820001000400020003000600230580700020004000300012000100120004000
660043047170091001400820001000400020003000600030576700020004000300012000100120004000
660042992270091001400820001000400020003000600230596700020004000300012000100120004000
660042973670091001400820001000400020003000600030576700020004000300012000100120004000
660042968170091001400820001000400020003000600030576700020004000300012000100120004000
660042974070091001400820001000400020003000600030584700020004000300012000100120004000
660042956470091001400820001000400020003000600030576700020004000300012000100120004000
660042956470091001400820001000400020003000600030576700020004000300012000100120004000
660042956670091001400820001000400020003000600030576700020004000300012000100120004000
660042956370091001400820001000400020003000600030576700020004000300012000100120004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4802051601815601768011232004216002280112320038160008240312480024320042856012220016000832001420024001296004280004160000320000100
4802041600535601228010432001216000680104320010160008240312480024320042856012220016000832001420024001296004280004160000320000100
4802041600535601228010432001216000680104320010160008240312480024320042856012220016000832001420024005496021080018160000320000100
4802041600545601228010432001216000680104320010160008240312480026229166456012420016000832001420024001296004280004160000320000100
4802041600635601288010432001816000680104320012160008240312480026320045056012220016000832001420024001296004280004160000320000100
4802041600545601228010432001216000680104320010160008240312480026320045056012220016000832001420024001296004280004160000320000100
4802061601565603088013232011416006280132320122160008240312480054320102256012220016000832001420024001296004280004160000320000100
4802041600535601228010432001216000680104320010160036240354480138320115056022020016003632007020024001296004280004160000320000100
4802041600535601228010432001216000680104320010160008240312480024320042856012220016000832001420024001296004280004160000320000100
4802041600535601228010432001216000680104320010160036240354480108320132856022020016003632007020024001296004280004160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4800251601515600808002232003616002280022320036160036240084480272296034656013220160036320070202400009600008000116000032000010
4800241600535600238001132001216000080010320000160000240030480072320018856001020160000320000202400009600008000116000032000010
4800241600475600178001132000616000080010320000160000240030480012320018856001020160000320000202400009600008000116000032000010
4800241600465600178001132000616000080010320000160000240030480012320018856001020160000320000202400009600008000116000032000010
4800251600945601268002832006416003480028320068160000240030480214320018856001020160000320000202400009600008000116000032000010
4800241600465600178001132000616000080010320000160000240030480012320018856001020160000320000202400009600008000116000032000010
4800241600465600178001132000616000080010320000160000240030480054320018856001020160000320000202400009600008000116000032000010
4800241600465600178001132000616000080010320000160036240084480228257709256013220160036320070202400129600428000416000032000010
4800241600485600268001432000616000680014320010160000240030480010320023256001020160000320000202400009600008000116000032000010
4800241600485600178001132000616000080010320000160000240030480010320023256001020160000320000202400009600008000116000032000010