Icestorm: LD4 (single, post-index, H) measurements

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
65005	29769	6033	1003	4028	1002	1002	4008	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29502	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29496	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29497	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29497	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29498	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29496	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29494	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29497	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0
65004	29658	6009	1001	4008	1000	1000	4000	1000	3000	3000	30576	6000	1000	4000	0	2000	8000	1001	1000	4000	0

Count: 8

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400205	160178	480160	80112	320037	80011	80112	320039	80004	240312	240012	2443650	480121	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160062	480124	80104	320017	80003	80104	320013	80018	240353	240053	2472573	480203	200	80018	320071	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240018	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400205	160090	480185	80117	320052	80016	80118	320067	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160036	640142	80017	80000	320000	100
400204	160053	480119	80104	320012	80003	80104	320012	80004	240312	240012	3200446	480120	200	80004	320015	200	160008	640030	80004	80000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400025	160318	480070	80022	320037	80011	80022	320039	80000	240030	240000	2656365	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400025	160090	480095	80027	320052	80016	80028	320067	80000	240030	240000	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240000	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240000	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240022	3200366	480010	20	80000	320000	20	160008	640030	80004	80000	320000	10
400024	160057	480017	80011	320006	80000	80010	320000	80000	240030	240015	3200370	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240006	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240000	3200366	480010	20	80000	320000	20	160036	640142	80017	80000	320000	10
400024	160054	480017	80011	320006	80000	80010	320000	80000	240030	240000	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10
400024	160046	480017	80011	320006	80000	80010	320000	80000	240030	240000	3200366	480010	20	80000	320000	20	160000	640000	80001	80000	320000	10

LD4 (single, post-index, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations