Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD4 (single, post-index, S)

Test 1: uops

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
65005300706041100740281006100640241000300030003057660001000400020008000100110004000
65004294836009100140081000100040001000300030003057660001000400020028008100210004000
65004295236005100140041000100040001000300030003057660001000400020008000100110004000
65004295096005100140041000100040001000300030003057660001000400020008000100110004000
65004294966005100140041000100040001000300030003057660001000400020008000100110004000
65004294866005100140041000100040001000300030003057660001000400020008000100110004000
65004295076005100140041000100040001000300030003057660001000400020008000100110004000
65004295006005100140041000100040001000300030003057660001000400020008000100110004000
65004294936005100140041000100040001000300030003057660001000400020008000100110004000
65004295036005100140041000100040001000300030003057660001000400020008000100110004000

Test 2: throughput

Count: 8

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205160323480160801123200378001180112320039800042403122400262593083480121200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100
400205160091480184801173200518001680118320067800042403122400123200446480120200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100
400204160063480119801043200128000380104320012800042403122400123200446480120200800043200152021600366401428001880000320000100
400204160055480119801043200128000380104320012800042403122400193200446480120200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600366401428001780000320000100
400204160053480119801043200128000380104320012800042403122400192602055480121200800043200152001600086400308000480000320000100
400204160053480119801043200128000380104320012800042403122400123200446480120200800043200152001600086400308000480000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025160151480065800223200328001180022320038800002400302400002656365480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010
400024160053480023800113200128000080010320000800002400302400003200366480010208000032000020160000640000800018000032000010