Icestorm: LDNP (D) measurements

Code:

  ldnp d0, d1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1166	2031	1	2030	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100157	70109	40101	10006	20002	30130	10015	20004	2669102	1779270	1048424	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	183049	124731	10443	86526	70825	949	101816
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60290	20028	10015	40008	20000	0	40100
60204	100051	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2669017	1779292	1048482	60110	30212	20008	10004	60282	20028	10015	40008	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2668898	1779138	1048344	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100152	70019	40011	10006	20002	30040	10015	20004	2669094	1779248	1049422	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20024	2669481	1779537	1072528	60083	30063	20029	10015	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2671895	1781120	1050567	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100045	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100152	70109	40101	10006	20002	30130	10015	20004	2669141	1779300	1048443	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100050	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60282	20028	10015	40008	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20024	2671915	1781216	1049623	60172	30245	20028	10015	60224	20008	10004	40001	20000	0	40100
60204	100104	70103	40101	10002	20000	30103	10003	20004	2669181	1779362	1048503	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100268	70019	40011	10006	20002	30040	10015	20004	2669269	1779400	1049537	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100144	70013	40011	10002	20000	30010	10000	20000	2669485	1779504	1049583	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20024	2669626	1779628	1049636	60082	30065	20028	10015	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80179	160131	101	160030	100	160008	300	488022	160108	200	160012	200	160012	1	160000	100
160204	80049	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160056	300	1258576	160156	200	160068	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	80211	160041	11	160030	10	160000	30	640218	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80068	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160068	0	1	160000	0	10
160024	80122	160011	11	160000	10	160008	30	1280190	160018	20	160012	20	160000	0	1	160000	0	10
160024	80054	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	0	1	160000	0	10

LDNP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations